A communication bus coupled between high performance devices, such as a communication bus providing for interconnection between integrated circuits (for “chip to chip” communication), Input/Output (I/O) devices, or between printed circuit boards via a connector, may need to operate at very high communication speeds. Moreover, interface logic and pin counts for implementing the bus may need to be minimized to reduce cost and complexity of the device in, or devices between, which the bus is located. Generally, a parallel bus will not meet the needs of many of today's applications due to being limited in operation to relatively slow data transmission speeds of one billion bits per second or less per parallel signal. A simple serial signal, although generally capable of operating at faster speeds than a parallel bus, will not meet today's needs as well, based at least in part on bandwidth demands. Applications today may require multiple serial signals operating in parallel to overcome these limitations. A parallel arrangement of serial signals is henceforth referred to as a “serial bus”.
A bus generally contains control lines and data lines. A synchronous bus generally is capable of operating at faster speeds than an asynchronous bus because no handshaking protocol is required. Additionally, because a fixed protocol typically is used for communicating data over the bus, the interface logic to implement the protocol is minimal and the bus can operate very fast relative to an asynchronous bus.
However, a synchronous bus includes a clock in the control lines and requires a fixed protocol for communicating data over the bus based on the clock. Thus, devices connected to the synchronous bus must operate at the same clock rate and participate in the fixed communication protocol. As a result, although many different synchronous bus architectures exist today, they are intimately tied to a predetermined communication protocol. This predetermined communication protocol can be a significant limitation, for example, when a device coupled to the bus has data formatted or framed according to different communication protocols, and is to transmit the data across the bus. Additionally, because of well known clock and data skew problems, the longer a synchronous bus, generally speaking, the slower the speed of the bus.
The Institute of Electrical and Electronics Engineers (IEEE) has proposed a standard for extending the operational distance of the 10 Gigabit Media Independent Interface (XGMII) parallel bus and reducing the number of interface signals between the Media Access Control (MAC) and Physical Layer Device (PHY) components in a 10 Gigabit Ethernet system (hereafter “10 GbE system” or simply “10 GbE”). The proposal, expected to be ratified in mid 2002, set forth in clauses 47 and 48 of the IEEE Draft P802.3ae, a supplement to the IEEE Std. 802.3, Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method and physical layer specifications, defines the electrical and functional characteristics for an optional 10 Gigabit Media Independent Interface (XGMII) eXtender Sublayer (XGXS) and a 10 Gigabit Attachment Unit Interface (XAUI) serial bus. (The “X” in “XAUI” represents the Roman numeral for ten and implies ten billion bits per second, that is, 10 gigabits per second, or 10 Gb/s.)
In a 10 GbE system implementing the optional XGMII extender, the XAUI bus receives a packet byte stream from the MAC or PHY, depending on the direction of packet flow, separates the packet byte stream into multiple serial binary digit (bit) streams for transmission over a corresponding number of physical communication paths (“lanes”), and encodes the bit stream to be transmitted on each lane using an industry standard 8B/10B coding scheme defined in U.S. Pat. No. 4,486,739 issued to Franaszek. The 8B/10B coding scheme translates an eight-bit byte of information into 10 binary digits for transmission over electromagnetic or optical transmission lines. Other well known serial signal and bus architectures use the 8B/10B coding scheme as well, such as InfiniBand (See InfiniBand™ Architecture Specification Release 1.0, Volume 2—Physical Specifications, Chapter 5: Link/Phy Interface), Fibre Channel (See ANSI NCITS T11 Fibre Channel Standards), and the 3 GIO high speed I/O interconnect serial bus architecture, promulgated by the Third Generation Peripheral Component Interconnect Special Interest Group (3 GIO PCI—SIG) (see http://www.pcisig.com).
However, the XAUI bus, heretofore, has not been implemented in a device in such a way as to be capable of supporting the transmission of one or more different data streams in a protocol independent manner over the bus. Some data streams, such as circuit switched, as opposed to packet switched, data streams, do not use or cannot take advantage of the 8B/10B coding scheme, for example, SONET (Synchronous Optical NETwork) data streams. (For a description of SONET, see ANSI T1.105: SONET—Basic Description including Multiplex Structure, Rates and Formats).